1. Technical Field
Various embodiments generally relate to a semiconductor device, and more particularly, to a technology for improving the timing skew of an input/output line.
2. Related Art
Semiconductor memory devices are being developed to increase the degree of integration and the operating speeds of the semiconductor memory devices. In order to increase operating speeds of the semiconductor memory devices a synchronous memory device has been developed. This synchronous memory device is capable of operating in synchronization with a clock signal received from outside the memory chip.
For example, a SDR (single data rate) synchronous memory device may be implemented whereby data is inputted and outputted through a single data pin during a single clock cycle. In the SDR synchronous memory device the input and output of the data is in synchronization with the rising edge of the clock signal.
However, the SDR synchronous memory device has difficulty operating with systems which require high speed operations. Accordingly, a DDR (double data rate) synchronous memory device may be implemented whereby data is consecutively inputted and outputted through each data input/output pin, in synchronization with the rising edge and the falling edge of a clock signal.
As such, a bandwidth at least two times wider than the conventional SDR synchronous memory device may be realized without increasing the frequency of a clock signal, and thus, a high speed operation may be achieved.
A DDR synchronous memory device adopts a multi-bit prefetch scheme in which multiple bits are internally processed at a time. The multi-bit prefetch scheme refers to a scheme in which data that is sequentially inputted are arranged in parallel in synchronization with a data strobe signal. Then the multi-bit data arranged in this way is stored at a time in a memory cell array by a write command which is inputted in synchronization with an external clock signal.